In the ongoing effort to provide higher device packing density and reduced chip size for metal-oxide-semiconductor field effect transistor (MOSFET) integrated circuits, alignment error between different pattern layers has been and continues to be a major obstacle. A number of design rules have been developed in an attempt to alleviate the alignment error problem, including maintaining a minimum contact-to-gate distance so as to avoid shorting, and maintaining a minimum contact-to-diffusion overlapping distance to avoid junction leakage. These and other exemplary design rules are intended to provide sufficient tolerance to mask misalignment and other process variations such that integrated circuits can be reliably manufactured. However, it is becoming increasing difficult to achieve further reductions in device dimensions while adhering to such design rules. A number of alternative approaches have therefore been developed, including processes for forming silicide-based self-aligned contacts which permit contact-to-gate overlap yet still provide adequate protection against shorting. A self-aligned contact provides greater tolerance to misalignment by allowing a contact to FET source or drain region to overlap with an adjacent gate region. The overlap is permissible because the self-aligned contact is formed in a manner which provides additional insulation between the contact and the gate such that shorting is prevented. Unfortunately, many of the presently available self-aligned contact formation processes are unduly complex and therefore unsuitable for use in practical semiconductor manufacturing applications.
U.S. Pat. No. 5,166,771 describes an exemplary silicide-based self-aligned contact and interconnect structure in which self-aligned source and drain contacts are permitted to overlap the gate. The self-aligned contacts are prevented from shorting to the gate by oxide spacers adjacent the gate and a protective silicon nitride layer overlying the gate. A local interconnect between a gate of one FET and a source or drain of an adjacent FET is also provided in the following manner. A double layer photoresist and multi-step etch process are used to expose the gate to be connected to the local interconnect, and a buried contact mask process is used to expose the source or drain to be connected to the local interconnect. The exposed silicon of the gate and source or drain regions is silicided by depositing a layer of sputtered titanium about 700 .ANG. thick and using rapid thermal annealing at 700.degree. C. in a nitrogen atmosphere to form a layer of TiSi coated by a thin layer of titanium nitride. Any unreacted titanium is stripped away using a wet chemical 5:1:1 solution of water, hydrogen peroxide and ammonium hydroxide which also attacks and removes the titanium nitride layer. A second rapid thermal annealing step at 900.degree. C. for 30 seconds in an atmosphere of ammonia converts the TiSi layer to a stable TiSi.sub.2 silicide coated by a thin layer of titanium nitride. A silicide layer is thus formed over the exposed gate and source or drain regions.
The local interconnect between these regions is then formed from an additional layer of polysilicon deposited over and contacting the silicide layer. The polysilicon layer is masked and etched using an etching process selective to the underlying silicide layer to thereby define the local interconnect. A 500 .ANG. layer of sputtered titanium is deposited over the etched polysilicon layer, followed by rapid thermal annealing at 640.degree. C. in a nitrogen atmosphere for 60 seconds to form a TiSi.sub.2 silicide local interconnect encapsulated by a thin titanium nitride film. The unreacted titanium and the titanium nitride film are stripped from the surface of the interconnect using the above-noted wet chemical solution. Although the processes disclosed in U.S. Pat. No. 5,166,771 may be used to provide both a silicide-based self-aligned contact to a source or drain region as well as a silicide-based local interconnect, separate process steps are required to form these different structures. This unduly complicates the self-aligned contact and local interconnect formation process and results in a costly, time-consuming and therefore impractical manufacturing operation. The disclosed processes also suffer from additional problems. For example, the use of a double layer photoresist to expose the poly gate region is inherently difficult to control.
A number of other known self-aligned contact processes fail to address adequately the formation of a local interconnect. U.S. Pat. No. 5,385,634 discloses an exemplary self-aligned contact formation process in which a gate electrode is sealed by a combination of a titanium nitride layer and a silicon nitride layer to prevent shorting with an overlapping source or drain contact. However, the disclosed process does not describe how a silicide-based local interconnect may be efficiently formed in conjunction with the self-aligned contact.
As is apparent from the above, a need exists for an improved process for forming silicide-based self-aligned contacts and local interconnects in a semiconductor device. The improved process should be relatively simple and easy to control, and therefore suitable for use in numerous practical semiconductor device manufacturing applications.